Many of today's integrated circuit (IC) designs are a complete system on a chip (SOC) that includes a processor core, multiple embedded memories, logic, I/O ports, etc. Embedded memories are the densest components in a SOC, accounting for up to 90% of the chip area. Memories are also the most sensitive to manufacturing process defects, making it essential to thoroughly test them in a SOC. As IC's are produced with greater levels of circuit density, efficient testing schemes that guarantee very high fault coverage while minimizing test costs and chip area overhead have become essential. However, as the complexity of circuits continues to increase, and as the number of memory circuits that can be packed into a chip of a given size increases, the need for efficient and cost effective testing of embedded memories has increased.
Built-in self-test (BIST), has become the method of choice for testing embedded memories, although it can also be used to test external memories. To use BIST for testing embedded memories, one or more BIST controllers are inserted within the SOC during the chip's design. The insertion may be done using a software design tool. One such tool is MBIST Architect™, offered by the assignee. The chip is then fabricated with the added BIST controllers. During testing of the fabricated chip, a BIST controller is instructed to supply a series of patterns to the ports of an embedded memory. These patterns, also called test algorithms, typically include but are not limited to march-type and checkerboard-type patterns that cause a memory to produce deterministic output data. The output data can be directly compared with input reference data from the controller. Alternatively, the output from the memory can be compressed and checked against a reference signature provided by the controller. In either case comparison generates a signal indicating that the memory passed or failed a test.
The time required to test memories is largely impacted by the size of the memory (i.e., larger memories take longer to test) and by a type of testing where the memories sit idle for a period of time. Examples of such tests where memories sit idle include retention tests, IDDQ tests, or other parametric tests. Such tests detect memory defects where a memory element appears to be functioning properly if written to and read from quickly, but over time the memory element loses its stored state. The loss of stored state could result from loss of charge on a charge-based storage element due to leakage currents. An example retention test fills memory with a pattern, waits a predetermined period of time (e.g., 100 milliseconds (ms)), and then reads the memory to check if the pattern is retained in memory. In the context of a retention test, the idle period may be called a “retention period”.
IDDQ testing is based on the premise that a fault-free integrated circuit draws very little supply current in a steady state. Unwanted shorts can cause a power and ground connection that increases current consumption under certain conditions. The current drawn by a faulty device is often several orders of magnitude higher than that drawn by a good device. Like the retention test, the IDDQ test requires a period of time where the memory is not accessed so that the appropriate steady state currents can be measured.
FIG. 1 shows an example prior art testing environment 10 for testing embedded memories that includes automated test equipment (ATE) 12 coupled to an IC 14. The IC 14 includes N BIST controllers (shown generally at 16) coupled in parallel. Each BIST controller is coupled to multiple memories to be tested. For example, a BIST controller 18 is coupled to the memories through data, address, and control lines. The memories 18, 20, 22 are shown having one or more output buses (shown generically at 26) coupled to the BIST controller 18. In the case where each memory has a separate output bus, the BIST controller 18 tests memories 20, 22, 24 in parallel and is called a “parallel” BIST controller. In the case where each memory has a shared output bus or the power budget prevents testing in parallel, the BIST controller 18 tests the memories one at a time (i.e., sequentially) and is called a “sequential” BIST controller.
To properly test the memories using retention or IDDQ tests, each BIST controller is coupled to a separate “hold” pin, such as hold pins 30, 32, on the IC 14. The hold pins are coupled to the ATE 12, which controls each hold pin individually. For example, when the ATE determines that BIST controller 18 is ready for a retention or IDDQ test, the hold pin 30 is asserted causing the BIST controller 18 to remain idle. The ATE then waits the desired amount of time and deactivates the hold pin allowing the BIST controller to continue the memory tests.
FIG. 2 illustrates a method for performing a retention test using BIST controller 18 as a sequential BIST controller to test multiple memories 20, 22, and 24. In order to test the memories, it is necessary for an ATE operator to perform an initial setup. For example, in process block 40, the ATE operator calculates when to assert the hold for each of three memories. The calculation generally involves multiplying the number of clock cycles necessary for a write operation by the number of memory addresses in each memory. Once the test starts, the BIST controller writes a pattern to the first memory (process block 42). After enough time has passed for the BIST controller to finish the writes to the first memory (as computed by the ATE operator), the ATE asserts the hold pin 30 (process block 44). With the hold pin activated, the BIST controller suspends accesses of memory for the retention period setup by the ATE operator. At the end of the retention period (for example, 100 ms) the ATE deactivates the hold pin to end the retention period (process block 46). The BIST controller then reads from the first memory and compares the read data to the previously written data (process block 48). The BIST controller then writes to the second memory (process block 50) and repeats the hold and read processes for the second memory (process blocks 52 to 56). This process is then repeated for the last memory (process blocks 58 to 64).
There are several disadvantages to the above-described memory testing technique. Foremost, the IC must allocate a hold pin for each BIST controller embedded in it. Multiple BIST controllers translate to multiple hold pins on the IC, which may require a larger, more expensive IC to accommodate the multitude of hold pins. Additionally, each hold pin is controlled by a separate channel on the ATE. Thus, larger and more expensive ATEs having sufficient channels are required for ICs having a large number of BISTs. There is also a computing burden placed on the ATE operator. The ATE operator has to perform a calculation for each memory. As noted above, the calculation is basically the number of clock cycles for a write multiplied by the number of addresses in the memory being tested. The calculation is a hardship not just because of the time factor, but also because the calculation must be very precise. An error of plus or minus one clock cycle in asserting the hold signal may lead to an error in the retention test.
A disadvantage that exists in prior sequential tests is that the overall testing time can be large because there is a separate retention period (process blocks 44, 52, and 60) for each memory tested. In a sample test the total memory access time might be 10 ms for each memory —30 ms for all three memories. Assuming the retention period is 100 ms, then the overall retention time is a relatively long 300 ms.
Therefore, there is a need for BIST technology that can perform retention tests and other tests using idle periods in an efficient manner.